Install uhdm with Homebrew, Nix

Project links

• Homepage
• Upstream docs
• Package manager page

Commands and aliases

• uhdm-cmp
• uhdm-dump
• uhdm-hier
• uhdm-lint

Project history

The public repository was created in 2019. The README describes UHDM's purpose as auto-generating a concrete C++ implementation of the SystemVerilog object model, a standard VPI facade, serialization and deserialization, visitor and listener traversal code, and elaboration logic.

UHDM's model is expressed in YAML files that follow the object-model portion of the SystemVerilog 2017 standard. The generated model can be populated by parsers such as Surelog or Verible and consumed by downstream tools such as Yosys and Verilator.

Release metadata shows v0.9.2 in 2022, v1.84 in 2024, and v1.85/v1.86 in 2025, reflecting its role as an evolving infrastructure library rather than a one-off command.

Adoption history

UHDM adoption is strongest in the open-source EDA and hardware-description-language ecosystem. Its README explicitly names Surelog and Verible as producers and Yosys and Verilator as consumers, placing it in the interchange layer between SystemVerilog front ends and analysis, synthesis, or simulation tools.

The supplied package data records UHDM in Homebrew and Nix. For package users, that makes a complex C++/Cap'n Proto/SystemVerilog infrastructure component installable without building the entire open-source EDA stack by hand.

How it is used

Developers use UHDM as a library and toolset for creating, serializing, inspecting, elaborating, and traversing SystemVerilog designs. The Homebrew package exposes utilities such as uhdm-dump, uhdm-cmp, uhdm-hier, and uhdm-lint.

The README describes uhdm-dump as a way to produce a human-readable view of a serialized UHDM design, and it describes listener and visitor patterns for client applications that need to traverse designs while the data model evolves.

Why package nerds care

UHDM is significant to package maintainers because it is plumbing for open-source hardware tooling. It pulls together generated C++ code, serialization, VPI compatibility, optional Python bindings, and downstream EDA consumers, so a working package can unblock multiple SystemVerilog workflows.

In the package-nerd niche, UHDM represents the move from monolithic EDA tools toward separately packaged interchange libraries that distributions can compose into parsers, linters, synthesizers, and simulators.

Timeline

• 2019: Public GitHub repository created.
• 2020: README linked a WOSET 2020 paper and presentation.
• 2022: v0.9.2 release published.
• 2024: v1.84 release published as a stable release.
• 2025: v1.86 release published.

Related projects

• The README names Surelog and Verible as producers of UHDM data.
• The README names Yosys and Verilator as consumers of UHDM data.
• The README also points to Cap'n Proto for serialization and the IEEE SystemVerilog 2017 object model as the standards basis.

Sources

• https://api.github.com/repos/chipsalliance/UHDM
• https://api.github.com/repos/chipsalliance/UHDM/releases?per_page=10
• https://github.com/chipsalliance/UHDM
• https://raw.githubusercontent.com/chipsalliance/UHDM/master/INSTALL.md
• https://raw.githubusercontent.com/chipsalliance/UHDM/master/README.md
• source_facts.executables
• source_facts.package-manager