Install sv2v with Homebrew

Project links

• Homepage
• Upstream docs
• Package manager page

Commands and aliases

• sv2v

Project history

The README says the project was created to provide a completely free and open-source SystemVerilog-to-Verilog converter, because existing approaches were often commercial or limited in scope. It was originally developed to target Yosys and to pass through SystemVerilog features that Yosys already supported.

The README also places the idea in a Carnegie Mellon University open-hardware research project, with collaboration beginning in January 2019. The GitHub commit history's oldest page records an initial commit on February 8, 2019, as a fork of Tom Hawkin's Verilog parser.

Adoption history

sv2v's adoption is niche but meaningful in open hardware workflows. The repository publishes prebuilt binaries for Ubuntu, macOS, and Windows, has a release series from v0.0.1 in January 2020 through v0.0.13 in March 2025, and is packaged in Homebrew according to the input facts.

How it is used

Typical use is to pass SystemVerilog source files to `sv2v` and receive converted Verilog on standard output or write adjacent `.v` files. The README emphasizes passing all source files together so packages, interfaces, and type parameters can be resolved across files, and documents include paths, library directories, macro definitions, conversion exclusions, and stdin input.

Why package nerds care

sv2v matters to package nerds because it makes an open HDL flow easier to install and automate. A packaged `sv2v` binary lets CI scripts, Makefiles, and Yosys-centered flows consume SystemVerilog projects without requiring proprietary conversion steps.

Timeline

• 2019: CMU open-hardware collaboration begins, according to the README.
• 2019: Initial public GitHub commit forks Tom Hawkin's Verilog parser.
• 2020: v0.0.1 release is published.
• 2025: v0.0.13 release is published.

Related projects

• sv2v is related to Yosys, Icarus Verilog, Haskell Stack, Tom Hawkin's Verilog parser, and open hardware build flows that need Verilog output from SystemVerilog sources.

Sources

• https://api.github.com/repos/zachjs/sv2v/commits?per_page=1&page=1044
• https://api.github.com/repos/zachjs/sv2v/releases?per_page=100
• https://github.com/zachjs/sv2v#readme
• input source_facts.package-manager