Install verilator with Homebrew, apk, apt, dnf, MacPorts, Nix, pacman, zypper

Project links

• Homepage
• Repository
• Upstream docs
• Package manager page

Commands and aliases

• verilator
• verilator_bin
• verilator_bin_dbg
• verilator_coverage
• verilator_coverage_bin_dbg
• verilator_gantt
• verilator_profcfunc

Project history

Verilator's roots go back to 1994 at Digital Equipment Corporation, where a Core Logic Group team led by Paul Wasson built technology to convert Verilog to C for Alpha-processor co-simulation. DEC released the source code in 1998, turning the internal tool into available open-source EDA infrastructure.

In 2001 Wilson Snyder took up the kit, added a SystemC mode, and packaged it as Verilator2. In 2002 he rewrote the tool from scratch in C++ as Verilator 3.000, producing large performance gains and setting the direction for the modern project under the Veripool umbrella.

The project kept expanding SystemVerilog and verification support, including major SystemVerilog and DPI additions in 2009. Verilator 4.000 in 2018 added multithreaded support, a milestone for using commodity multi-core hosts to accelerate hardware simulation. In 2019 Verilator joined the CHIPS Alliance, reflecting its role in the open-source silicon ecosystem.

In the Verilator 5 era, the project added a more IEEE-compliant scheduler and delay semantics, addressing historical limitations while preserving its compiled-simulation identity. Current documentation presents it as a fast SystemVerilog simulator, lint tool, C++/SystemC model generator, and JSON-emitting front end for other tools.

Adoption history

Verilator's earliest adoption came from engineering teams that needed fast executable models and were willing to integrate HDL with C++ or SystemC testbenches. Secondary histories and the Verilator FAQ describe use across academic research, open-source projects, major silicon companies, and large organizations such as CERN.

The rise of open hardware made Verilator more central. Projects in the RISC-V, OpenRISC, CHIPS Alliance, and education communities use it because it is packageable, automatable, and free software, making it viable in CI where proprietary EDA licensing is impractical or impossible.

Commercial adoption grew because Verilator can turn synthesizable RTL into fast simulation artifacts for long regressions and software bring-up. It does not replace every feature of event-driven commercial simulators, but it occupies a powerful niche where speed, openness, and integration with normal C++ tooling matter.

How it is used

Package users invoke `verilator` on Verilog or SystemVerilog sources to generate C++ or SystemC, compile the generated model with a C++ testbench, and run the resulting executable. Common flags select C++ output, lint-only checks, tracing, SystemC output, coverage, multithreading, and build integration.

Verilator is used for linting RTL, building cycle-accurate simulators for CPU cores and SoCs, running firmware against hardware models, profiling generated simulation code, collecting coverage, and integrating HDL models into larger C++ or SystemC environments. Its companion tools such as `verilator_coverage`, `verilator_gantt`, and profiling helpers support those workflows.

Why package nerds care

Verilator is one of the rare EDA tools that feels native to ordinary open-source package workflows: install it, run it in CI, version the RTL and testbench, and avoid license-server friction. For hardware developers, that makes the Homebrew formula more than convenience; it is an on-ramp to serious open silicon verification.

Timeline

• 1994: DEC's Core Logic Group develops the original Verilog-to-C technology for Alpha co-simulation.
• 1998: DEC releases the source code.
• 2001: Wilson Snyder packages the technology as Verilator2 and adds SystemC mode.
• 2002: Verilator 3.000 is rewritten in C++ with major performance gains.
• 2009: Major SystemVerilog and DPI support lands.
• 2018: Verilator 4.000 introduces multithreaded support.
• 2019: Verilator joins the CHIPS Alliance.
• 2022 onward: Verilator 5 work improves IEEE scheduling and delay semantics while retaining the compiled-model architecture.

Related projects

• Verilator is related to Icarus Verilog, CXXRTL/Yosys, GHDL, commercial simulators such as Synopsys VCS, Siemens Questa/ModelSim, and Cadence Xcelium, and open-hardware projects such as OpenRISC and RISC-V cores. Compared with Icarus Verilog it is usually chosen for speed and C++ integration; compared with commercial tools it is chosen for openness and packageability.

Sources

• https://abopen.com/news/wilson-snyder-officially-launches-verilator-4-0-at-orconf-2018/
• https://en.wikipedia.org/wiki/Verilator
• https://github.com/verilator/verilator
• https://verilator.org/guide/latest/changes.html
• https://verilator.org/guide/latest/contributors.html
• https://verilator.org/guide/latest/languages.html
• https://veripool.org/guide/latest/faq.html
• https://veripool.org/papers/
• https://www.veripool.org/verilator/