yosys を Homebrew, apk, apt, dnf, Nix, pacman, scoop でインストール

プロジェクトリンク

• ホームページ
• リポジトリ
• 上流ドキュメント
• パッケージマネージャページ

コマンドとエイリアス

• yosys
• yosys-abc
• yosys-config
• yosys-filterlib
• yosys-smtbmc
• yosys-witness

プロジェクトの歴史

Yosys began as Claire Wolf's BSc thesis project to support synthesis for a coarse-grained reconfigurable architecture, then expanded into general infrastructure for synthesis research. The Yosys documentation preserves that origin and describes the first documentation as a bachelor thesis at Vienna University of Technology.

The 2013 Austrochip paper framed the problem plainly: commercial ASIC and FPGA tools dominated synthesis, but closed internals and encrypted intermediate formats made them poor bases for research and reproducibility. Yosys answered that gap with an extensible open framework: frontends convert HDL into RTLIL, passes transform and analyze it, and backends write the resulting design.

By the late 2010s Yosys had moved from research artifact to central open hardware infrastructure. Contemporary documentation describes full support for the synthesizable subset of Verilog-2005, use in hobbyist, academic, and commercial settings, and a role in open FPGA and ASIC flows. YosysHQ now maintains Yosys and related tools, with commercial extensions available through Tabby CAD Suite while the open tool remains the ecosystem core.

採用の歴史

Yosys adoption followed the needs of open hardware. It became the synthesis engine in flows where proprietary vendor tools were unavailable, undesirable, or too opaque: Lattice iCE40/ECP5 flows with nextpnr, OpenLane/SkyWater open ASIC experiments, formal verification frontends, and education/research workflows that needed reproducible tooling.

AB Open described Yosys as first launched in 2012 and as the first full-featured open-source package for Verilog HDL synthesis. That claim captures why it mattered: before Yosys, open-source HDL tooling had simulators and pieces of logic optimization, but not a broadly useful, scriptable Verilog synthesis framework packaged for everyday developers.

Its adoption also comes from being a framework rather than a single hard-coded flow. Users can run the interactive shell, write synthesis scripts, add passes, target multiple FPGA families, emit formal solver formats, and combine it with related YosysHQ tools such as SBY, EQY, MCY, and SCY.

使われ方

Typical use starts with reading Verilog or SystemVerilog, checking hierarchy, running passes such as proc, opt, fsm, memory, techmap, and abc, then writing Verilog, BLIF, JSON, BTOR, SMT2, or another backend format. The README emphasizes both interactive use and script files, which made synthesis flows reviewable and reproducible.

For FPGA work, Yosys handles synthesis while nextpnr or vendor tools handle place-and-route. For ASIC-style open flows, Yosys performs the synthesis portion before later physical-design stages. For formal workflows, it converts HDL into solver-oriented representations and underpins tools such as SBY.

Package-manager users install it as a command-line suite: yosys for the shell and scripts, yosys-config for build integration, yosys-smtbmc for model checking workflows, and auxiliary binaries such as yosys-abc where packaged.

パッケージ好きにとっての重要性

Yosys is one of the clearest examples of package managers changing who can participate in hardware design. A synthesis tool that once would have meant vendor installers and license servers can be installed, scripted, pinned in CI, built from source, and combined with other open packages.

It also made hardware compilation feel more like software compilation: inspectable intermediate representations, pass pipelines, text scripts, plugins, tests, and reproducible command-line output. That is why package collections treat it as core developer tooling rather than as an exotic EDA side package.

タイムライン

• 2012: Yosys is publicly launched as an open Verilog synthesis suite.
• 2013: The Yosys thesis/paper documents its design, RTLIL flow, extensibility, and reproducibility motivation.
• 2018: Public coverage describes Yosys as a popular open synthesis framework with growing platform support.
• 2020s: Yosys becomes central to open FPGA flows, OpenLane-style open ASIC work, and YosysHQ formal tools.

Related projects

• Berkeley ABC is used by Yosys for combinational logic minimization and technology mapping.
• nextpnr is the open place-and-route tool commonly paired with Yosys for FPGA bitstream flows.
• OpenLane uses Yosys for the synthesis stage in open ASIC flows.
• SBY, EQY, MCY, and SCY are YosysHQ tools built around Yosys for formal verification, equivalence checking, mutation coverage, and trace workflows.
• OSS CAD Suite and Tabby CAD Suite distribute Yosys with related open and commercial EDA tooling.

ソース

• https://abopen.com/news/clifford-wolf-launches-yosys-open-synthesis-suite-0-8/
• https://api.github.com/repos/YosysHQ/yosys
• https://github.com/YosysHQ/oss-cad-suite-build
• https://github.com/YosysHQ/yosys
• https://yosyshq.net/yosys/files/yosys-austrochip2013.pdf
• https://yosyshq.readthedocs.io/projects/yosys/en/0.41/introduction.html